1. Field of the Invention
The present invention relates to a memory controller for a DDR (Double Data Rate) memory and a semiconductor device mounted with the memory controller.
2. Description of Related Art
As a type of an SDRAM (Synchronous Dynamic Random Access memory), a DDR (Double Data Rate)-SDRAM is known which can transfer data at high speed. Hereinafter, the DDR-SDRAM is referred to as a “DDR memory”. In addition, a memory controller for the DDR memory is hereinafter referred to as a “DDR memory controller”.
In the high-speed data transfer between the DDR memory and the DDR memory controller, a special signal called a “strobe signal” is used. Specifically, a data sending side outputs the strobe signal together with a data signal. The strobe signal repeats a toggle operation between a high level and a low level each time the data signal is outputted. However, it is a different signal from a clock signal. A data receiving side receives the data signal in response to not the clock signal but the received strobe signal. For example, in data read, the DDR memory outputs the strobe signal in addition to the data signal indicating read data. In response to the received strobe signal, the DDR memory controller latches a received data signal at timings of a rising edge and a falling edge of the strobe signal. At this time, in order to latch the data signal in a stable state, the DDR memory controller delays the received strobe signal and latches the data signal in response to the delayed strobe signal. As a method for delaying the strobe signal, a method of using a DLL (Delay Locked Loop) circuit and a delay circuit is well known, as shown in Japanese Patent Application Publication (JP-P2004-220643A, related art 1) and DesignLine, Volume 8, Issue 3, 3Q99, Micron Technology Inc. (related art 2).
FIG. 1 shows a DDR memory controller 140 shown in the related art 1. The DDR memory controller 140 receives a data signal DQ and a strobe signal DQS outputted from a DDR memory. The data signal DQ is a signal of 8 bits (DQ0 to DQ7). As shown in FIG. 1, the DDR memory controller 140 includes a slave delay circuit 110, a master DLL circuit 120, and a gear ratio logic circuit 130.
The slave delay circuit 110 is a circuit for delaying the strobe signal DQS received from the DDR memory. Specifically, the slave delay circuit 110 has a variable delay circuit whose number of delay stages is changed based on a delay code, and delays the strobe signal DQS by a delay time tSD determined based on the number of delay stages. A group of flip-flops latch the data signal DQ In response to a rising edge or a falling edge of the strobe signal DQS outputted from the slave delay circuit 110. In order to latch the data signal DQ in a steady state, the number of delay stages (the delay time tSD) is specifically set so that a phase of the strobe signal DQS can be shifted by approximately 90 degrees. In other words, the delay code is determined so that the phase of the strobe signal DQS can be shifted by approximately 90 degrees.
Here, it should be noted that a characteristic of a delay element of the delay circuit depends on a temperature and a manufacture variation. That is, the delay time tSD may vary depending on the temperature and the manufacture variation even in case of an identical delay code (the number of delay stages). In order to align the delay time tSD to a same time length for semiconductor chips, it is required to adjust (trim) the delay code for each of the semiconductor chips. A configuration for performing such trimming of the delay code is realized by the master DLL circuit 120 and the gear ratio logic circuit 130.
The master DLL circuit 120 receives an operation clock signal CK of the DDR memory as a reference clock signal, and calculates the number of delay stages at which a phase of the reference clock signal CK is shifted by 360 degrees (a single period). Specifically, the master DLL circuit 120 has a variable delay circuit, a phase detector, and a delay controller. The variable delay circuit has a same configuration as that of the above-mentioned slave delay circuit 110, and the number of delay stages changes depending on a control signal outputted from the delay controller. The variable delay circuit receives the reference clock signal CK and delays the reference clock signal CK for the delay time tCK based on the set number of delay stages. The reference clock signal CK that is not delayed and the delayed reference clock signal CK outputted from the variable delay circuit are supplied to the phase detector. The phase detector compares the phases of the two reference clock signals CK and outputs a comparing result to the delay controller. The delay controller changes the control signal based on the comparing result and varies the number of delay stages in the variable delay circuit. According to such a configuration, the number of delay stages realizing a delay of the reference clock signal CK for a single period can be determined.
The gear ratio logic circuit 130 divides the number of delay stages for realizing the delay of the reference clock signal CK for the single period by “4”. As the result, the number of delay stages is calculated when the phase of the reference clock signal CK can shift by 90 degrees. A signal indicating the calculated number of delay stages is the delay code in the semiconductor chip. The slave delay circuit 110 sets the number of delay stages on the basis of the determined delay code and delays the strobe signal DQS for the delay time tSD.
According to this, the master DLL circuit 120 and the gear ratio logic circuit 130 performs the trimming of the delay code for each of the semiconductor chips. As the result, the delay time tSD of the strobe signal DQS in the slave delay circuit 110 will be aligned for the respective semiconductor chips. That is, the temperature of an operation environment and the manufacture variation can be dealt with.
In recent years, it is desired to operate the DDR memory at various operation frequencies. For example, it is desired to decrease the operation frequency of the DDR memory to reduce the consumed power when data is not read so frequently. According to the configuration shown in FIG. 1, when the operation clock signal CK of the DDR memory is changed, the above mentioned delay code is accordingly reset to an appropriate value. Thus, the DDR memory controller can stably take the data signal DQ therein even when the frequency of the operation clock signal of the DDR memory is changed.
However, resetting (re-trimming) of the delay code takes a certain amount of time. Accordingly, during the resetting of the delay code, the DDR memory is required to be set to a waiting state, resulting in deterioration of throughput. That is, a temporal overhead caused by the resetting of the delay code according to a change of the operation frequency of the DDR memory causes the deterioration of throughput.